By Yu-Tsang/Carven Chang
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Additional info for Advance HDL Design Training On Xilinx FPGA
CIC HDL Flow projects do not require the designation of a top-level design until synthesis. Only VHDL or Verilog source files can be added to an HDL Flow project. VHDL and Verilog source files can be created by the HDL Editor, Finite State Machine Editor, or other text editors. When you initiate the synthesis phase, you designate one of the project's entities (VHDL) or modules (Verilog) as the top-level of the design. The list of entities and modules is automatically extracted from all the HDL source files added to the project.
Click Next. Note:For top-level ABEL designs, you must use the Schematic Flow. 02/XLNX_HDL flow-10 CIC Creating the Design III ! In the Design Wizard - Name window, enter the name of your design file. Click Next. Define your ports in the Design Wizard-Ports window by clicking NEW, entering the port name, and selecting its direction. Click Finish. The Wizard creates the ports and gives you a template (in VHDL or Verilog) in which you can enter your design. 02/XLNX_HDL flow-11 CIC Creating the Design IV !
Create / Edit Timing Subpath ! Create a new subpath by clicking the right mouse button on either the appropriate primary path or any subpath of the primary path, and selecting New Sub path. 02/XLNX_HDL flow-28 Sub Path II ! CIC In the Create/Edit Timing Sub Path dialog box, enter the desired delay, and then double-click all of cells making up the subpath. The controls below each list give an alternate way of adding named cells to the list using global-style regular expressions (similar to filename wildcards).